Gw-instek GDM-8246 Programming Manual Manuel d'utilisateur télécharger pdf (Page 24)

GDM-8246 MULTIMETER

PROGRAMMER MANUAL

⎯ 46 ⎯

7. STATUS AND ERROR REPORTING

A set of status registers allows the user to quickly determine the

DMM’s internal processing status. The status register, as well as the

status and event reporting system, adhere to SCPI recommendations.

Structure of System

The sketch of the status and event reporting system is showed as

figure 7. Each component of the sketch represents a set of registers and

queues that can read, report, or enable the occurrence of certain events

within the system.

If a specific event in the DMM sets a bit in a status register, reading

which can tell you what types of events have occurred.

Each bit in the status register corresponds to a bit in an enable register;

the enable bit must be high for the event to be reported to the Status Byte

A Service Request (SRQ) is the last event to occur. The SRQ requests an

interrupt on the GPIB to report events to the system controller.

Status Registers

There are two kinds of status registers are included to the DMM.

z OPERation Status Registers ( CONDition, EVENt, and ENABle)

z QUEStionable Status Registers (CONDition, EVENt, and ENABle)

The lower level nodes: QUEStionable and OPERation each have three 16

bits registers: CONDition, EVENt, and ENABle. Figure 8 shows the

sequential relationship between these three types of registers and the

commands that relate to each register.

GDM-8246 MULTIMETER

PROGRAMMER MANUAL

⎯ 47 ⎯

Frequency Null Sense

Not Used

Limit Test Fail HI

Limit Test Fail LO

Capacitance Overload

Ohm Overload

Not Used

Voltage Overload

Current Overload

QUEStionable Status

Not Used

OPERation Status

Not Used

Command Error

Power On

User

Request

Execution Error

Device Dependent

Error

Query Error

Not Used

Standard Event Status Registers

Operation Complete

ESB

RQS/MSS

Not Used

Status Byte Register

Not Used

Summary of IEEE 488.2 Status Structure Registers

E/E

Not Used

QUES

OPER

SRQ

Error/Event Queue

Output Queue

Figure 7. A graphic representation of the status registers and their connections.

1 2 ... 19 20 21 22 23 24 25 26 27 28

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