
STATUS REGISTERS
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The Questionable Status Condition Register
indicates the status of the electronic load. If a bit is
set in the Condition register (OC, OV, OP, RV)
indicates that the event is true. Reading the
condition register does not change the state of the
condition register.
The PTR/NTR (Positive/Negative transition)
register determines the type of transition
conditions will set the corresponding bit in the
Event Registers. Only the Channel Status Register
and Questionable Status Register can be transition
programmed.
The PTR/NTR Register will dictate the type of
transition conditions will set the corresponding
bits in the Event Register. If the Event Register is
read, it will be cleared to 0.
The Enable Register is used to determine which
channel events will be used to set the QUES bit of
the Status Byte Register.
Output Queue
The Output queue stores output messages in a
FIFO buffer until read. If the Output Queue has
data, the MAV bit in the Status Byte Register is set.
Output Queue
Data1 Data2 Data3 Data4 DataNData5
Data inData out
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